Problems can occur in high-speed bidirectional buses between two semiconductor chips when the transmission line electrical length exceeds the rise-time or fall-time of the signal. Setup times may not be met for the first bit received after a bus turnaround. The problem arises when the bus electrical design is such that the same electrical condition is used both for termination of the bus in its characteristic impedance and for driving one of the two logic levels. With buses of this design, when a bus turnaround occurs, the driving chip which is relinquishing the bus turns off its output driver and turns on its terminator, and the chip which is taking over the bus turns on its output driver.
When one chip drives the bus at the non-terminating electrical level (for example, a zero) and relinquishes the bus, at the end of its last bit time, the former driving chip will turn on its bus termination in preparation for receiving signals from the other chip. Since the same electrical condition is used both for termination of the bus in its characteristic impedance and for driving one of the logic levels, the chip that is relinquishing the bus actually drives an electrical signal transition (for example, from a zero to a one) down the bus during the transition period. This signal can be thought of as a transitional value. If the new bus master chip drives the opposite logic level (for example, a zero) during this transition time, the value driven by the new chip will not be seen at the relinquishing chip in time to be properly detected. This is because the relinquishing chip continues to see the transitional value that it is driving until that transitional value travels to the new bus driver and is reflected back to the relinquishing chip.
The length of the transmission time between the chips determines the length of time the relinquishing chip will receive the transition value and, therefore, the time during which it will be unable to detect the correct value from the new driving chip.
Prior solutions to this problem have been to shorten the distance between the two semiconductor chips or to slow down the clock to ensure the data arrives timely and accurately. For example, the clock could be slowed down to around 440 megahertz versus the more ideal operating frequency of 500 megahertz.
Another prior solution involves reducing the delay associated with the circuit logic through which the signal travels.
Another prior solution is to add an idle cycle as the first bus cycle after bus turnaround, thus ignoring bus activity during this cycle at the expense of decreased performance.